1. Field of the Invention
The present invention relates to methods for fabricating integrated circuits with trenches. More particularly, the present invention relates to methods for forming trenches with multiple depths to isolate active device areas on SOI fabricated semiconductor wafers.
2. Description of the Related Art
Semiconductor wafer fabrication involves a series of processes used to create semiconductor devices and integrated circuits (ICs) in and on a semiconductor wafer surface. Fabrication typically involves the basic operations of layering and patterning, together with others such as doping, and heat treatments. Layering is an operation used to add thin layers of material (typically insulator, semi-conductor or conductor) to the surface of the semiconductor wafer. Patterning is an operation that is used to remove specific portions of the top layer or layers on the wafer surface.
Conventional or bulk semiconductor devices are formed in semiconductor material by implanting a well of either P-type or N-type conductivity in a silicon substrate wafer of the opposite conductivity. Gates and source/drain diffusions are then manufactured using commonly known processes. These form devices known as metal-oxide-semiconductor (MOS) field effect transistors (FETs). When a given chip uses both P-type and N-type, it is known as a complimentary metal oxide semiconductor (CMOS). Each of these transistors must be electrically isolated from the others in order to avoid shorting the circuits.
In order to deal with the junction capacitance and “off state” leakage problem as well as obtain reduced size, semiconductor-on-insulator technology (SOI) has emerged. This technology constructs silicon devices, such as transistors, on a thin Si film formed on an insulative substrate rather than on a conventional silicon substrate. Silicon-on-insulator technology provides superior electrical isolation between adjacent components, reduces junction capacitance, and reduces the power consumption.
SOI wafers may be formed in various ways including from a bulk silicon wafer by using conventional oxygen implantation techniques to create a buried oxide layer at a predetermined depth below the surface of the silicon. The implanted oxygen oxidizes the silicon into insulating silicon dioxide in a normal distribution pattern centered at the predetermined depth to form the buried oxide layer. MOSFET (metal oxide semiconductor field effect transistors) transistors formed on SOI substrates also may be able to achieve higher speed operation with higher drive currents, when compared with MOSFETs formed on conventional bulk silicon substrates. One problem with forming field effect transistors on an SOI wafer is the floating body effect. That is, isolation structures extending to the insulating layer prevent the various devices on the substrate from making contact with the body of the substrate.
Isolation structures, which are areas that prevent the active devices from interfering with each other, are important for device operation. A variety of techniques have been developed to isolate devices in integrated circuits including shallow trench isolation (STI) and conventional LOCOS isolation. Shallow trench isolation (STI) is more predominant for deep sub-micron technology, because it is free from bird's beak encroachment, field oxide thinning and leakage due to punch through.
In conventional CMOS technology shallow trenches are used to isolate devices partially from each other while allowing the body contact to all the devices. However, in SOI-CMOS technology the trench isolation completely separates devices from each other and does not permit a body contact. In order to partially implement and benefit from some of the SOI technology's advantages, deep trenches can be formed to completely isolate some of the devices from the others (e.g., NMOS from PMOS), while a shallower trench is used for lateral isolation of the device junctions. This configuration still leaves a connection path to the device substrate and permits implementation of transistors on SOI substrate with a weak body tie.
Unfortunately, creation of two different trench depths on the same substrate is problematic. One conventional method creates two different trench depths for the above purpose by first patterning and etching one trench depth in the substrate followed by another patterning and etch step to define the second trench depth in the locations required for complete isolation. However, patterning the second trench after defining the first trench is difficult, especially if the two trenches are contiguous or overlap. Significant topography variation between the depth of the first trench and the surface of the substrate makes resist coverage difficult. The variation in the resist layer thus makes lithographic printing for the second trench difficult. Moreover, alignment between layers using alignment marks is very difficult while fabricating dual trenches in this manner. The presence of the photoresist interferes with alignment of the second layer relative to the first layer because the non-planar resist diffracts the incoming light causing an apparent shift in the alignment mask position.
Unfortunately, there is no conventional process that is currently specifically capable of overcoming the alignment and patterning issues in a satisfactory manner. Accordingly, what is needed is an improved process for formation of dual trench depths to completely isolate an individual or a group of devices from others while allowing a partial body contact to devices in SOI technology and which further provides inter layer alignment capabilities.